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翻訳と辞書　辞書検索 [ 開発暫定版 ] スポンサード リンク PowerPC e500 ： ウィキペディア英語版 PowerPC e500 The PowerPC e500 is a 32-bit Power Architecture-based microprocessor core from Freescale Semiconductor. The core is compatible with the older PowerPC Book E specification as well as the Power ISA v.2.03. It has a dual issue, seven-stage pipeline with FPUs (from version 2 onwards), 32/32 KiB data and instruction L1 caches and 256, 512 or 1024 KiB L2 frontside cache. Speeds range from 533 MHz up to 1.5 GHz, and the core is designed to be highly configurable and meet the specific needs of embedded applications with features like multi-core operation interface for auxiliary application processing units (APU). e500 powers the high-performance PowerQUICC III system on a chip (SoC) network processors and they all share a common naming scheme, ''MPC85xx''. Freescale's new QorIQ is the evolutionary step from PowerQUICC III and will also be based on e500 cores. == Versions == There are three versions of the e500 core, namely the original ''e500v1'', the ''e500v2'' and the ''e500mc''. A 64-bit evolution of the e500mc core is called the e5500 core and was introduced in 2010. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「PowerPC e500」の詳細全文を読む スポンサード リンク 翻訳と辞書 : 翻訳のためのインターネットリソース Copyright(C) kotoba.ne.jp 1997-2016. All Rights Reserved.